The invention relates to a memory cell configuration with memory elements having a layer structure with a giant magnetoresistive effect (GMR).
The term GMR element is used in the pertinent art for layer structures which have at least two ferromagnetic layers and a non-magnetic layer arranged in between and exhibit the so-called GMR (giant magnetoresistive) effect. The GMR effect encompasses the fact that the electrical resistance of the GMR element is dependent on whether the magnetization in the two ferromagnetic layers is oriented in a parallel or antiparallel.
It has been proposed (see, for example, D. D. Tang et al., IEDM 95, pages 997-99; D. D. Tang et al., IEEE Trans. on Magnetics, Vol. 31, No. 6, 1995, pages 3206-08; F. W. Patten et al., Int. Non Volatile Memory Technology Conf., 1996, pages 1-2) to use such GMR elements as memory elements in a memory cell configuration. For this purpose, GMR elements in which the magnetization direction of one ferromagnetic layer is fixed for example by an adjacent antiferromagnetic layer are used as memory elements. The memory elements are connected in series via bit lines. Word lines run transversely with respect to the latter and are insulated from both the bit lines and the memory elements. Signals applied to the word lines cause a magnetic field as a result of the current flowing in the word line. The magnetic field influences the memory elements situated underneath. In order to write information, signals are applied to a bit line and a word line, which intersect above the memory cell to be written to. At the point of intersection, the signals cause a magnetic field which is sufficient for the magnetization reversal. In order to read the information, a pulsed signal is applied to the word line. The pulsed signal switches the relevant memory cell back and forth between the two magnetization states. The current through the bit line is measured and the resistance of the corresponding memory element is determined from the measured current. S. Tehrani et al. IEDM 96, pages 193 ff., have proposed using a GMR element having ferromagnetic layers of different thicknesses as the memory element. The magnetic field for writing information is dimensioned such that it only influences the magnetization in the thinner of the two ferromagnetic layers. The magnetization in the thicker of the two ferromagnetic layers remains uninfluenced by it.
It is an obvious drawback that the read-out operation with pulsed signals requires an increased outlay on circuitry in these memory cell configurations.
It is accordingly an object of the invention to provide a memory cell configuration with GMR elements, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which can be read with a reduced outlay on circuitry.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration, comprising:
a plurality of substantially parallel word lines and a plurality of substantially parallel bit lines running transversely to the bit lines; memory elements having a layer structure with a giant magnetoresistive effect, the memory elements being respectively connected between one of the word lines and one of the bit lines and having a higher resistance than the word lines and the bit lines;
a sense amplifier connected to each of the bit lines for regulating a potential on a respective the bit line to a reference potential and outputting an output signal.
In accordance with an added feature of the invention, the sense amplifier has a feedback operational amplifier.
In other words, the memory cell configuration has word lines bit lines traversing the word lines. Memory elements having a layer structure with a very large magnetoresistive effect (GMR), that is to say GMR elements, are provided. The GMR elements are respectively connected between one of the word lines and one of the bit lines and have a higher resistance than the word lines and the bit lines. The bit lines are each connected to a sense amplifier by means of which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off. In order to read this memory cell configuration, all the word lines which are not selected are put at the reference potential. A signal with a different potential is applied to the selected word line. A current path from the selected word line to all the bit lines is closed as a result of this. The resistance of the memory element situated at the point of intersection of the word line with the respective bit line can be determined from the output signal at the respective sense amplifier, the electrical characteristic parameters of the sense amplifier, such as the feedback resistance, for example, and the reference potential and the bit line resistance. A pulsed signal is not necessary, therefore, in order to read this memory cell configuration.
The sense amplifier preferably has a feedback operational amplifier. The non-inverting input of the operational amplifier is connected to reference potential, for example to ground. The bit line is connected to the inverting input. If the reference potential is 0 volts, then this operational amplifier ensures that 0 volts are present on the bit line. The output signal of the operational amplifier is a measure of the resistance of the selected memory element.
All known GMR elements are suitable as the memory element, provided that they have a higher resistance than the bit line and the word line in both magnetization states. The GMR effect is greater if the current flows perpendicularly through the layer stack than if the current flows in parallel into the layers.
In accordance with an additional feature of the invention:
the memory elements each have two ferromagnetic layers and a non-magnetic layer arranged between the two ferromagnetic layers;
an antiferromagnetic layer is disposed adjacent to one of the ferromagnetic layers and determines a polarization direction of a magnetization in the adjacent ferromagnetic layer; and
the memory elements each have two magnetization states.
It is advantageous to use an insulating, non-magnetic layer since the GMR effect, which is brought about by a spin-polarized tunneling current through the insulating, non-magnetic layer arranged between the two ferromagnetic layers, is much greater in these structures than if a non-insulating, non-magnetic layer is used. The different resistances assigned to two different logic values 0 and 1 in the memory cell configuration can be better distinguished as a result of this.
As an alternative, the memory elements may each have two ferromagnetic layers and a non-magnetic layer arranged in between, one of the ferromagnetic layers being thicker than the other ferromagnetic layer or the ferromagnetic layers being formed from different materials with different magnetic properties, or have a non-magnetic, non-insulating layer.
Materials containing at least one of the elements Fe, Ni, Co, Cr, Mn, Gd are suitable, inter alia, for the ferromagnetic layers. The thickness of the ferromagnetic layers is at most 20 nm and preferably lies in the range between 2 and 10 nm. The oxides Al2O3, NiO, HfO2 or TiO2, NbO, SiO2 are all suitable as insulating material for the non-magnetic layer, which acts as a tunnelling insulator. Cu or Ag is suitable as non-insulating material for the non-magnetic layer. The thickness of the non-magnetic layer lies in the range between 1 and 4 nm, preferably between 2 and 3 nm.
In order to write information to one of the memory elements, a respective signal is applied to the associated word line and to the associated bit line. As a result, a current flows via the word line and the bit line and induces a magnetic field in each case. At the point of interception of the word line and bit line, the total magnetic field resulting from superposition of the two magnetic fields is large enough to ensure magnetization reversal of the memory element situated there. Outside the point of intersection, the individual magnetic fields are too small for magnetization reversal of the memory elements situated there.
In applications where an increased magnetic field is necessary or desirable for the purpose of writing, it lies within the scope of the invention to additionally provide write lines running essentially parallel to one another, which write lines run parallel to the bit lines, for example. These write lines are insulated from the word lines and the bit lines. By applying a signal to the corresponding write line, it is possible to amplify the magnetic field at the point of intersection with the selected word line and thus to support the writing operation.
The memory cell configuration is suitable as a magnetic RAM (MRAM).
Furthermore, the memory cell configuration can be operated as an associative memory. For this purpose, a respective threshold value element is provided with regard to the bit lines, which element is connected to the output of the sense amplifier of the respective bit line.
In an associative memory, as disclosed for example in K. Goser et al., IEEE Micro, 9 (1989) 6, pages 28-44, an input signal is applied simultaneously to all the word lines. The input signal has as many places as word lines. The current is summed at each of the bit lines and the output signal is formed with a threshold value element. In the associative memories disclosed in Goser et al., IEEE Micro, 9 (1986) 6, pages 28-44, the memory cell comprises only a conventional resistor or a transistor and is connected between intersecting word lines and bit lines. These conventional resistors and transistors cannot be altered during operation, with the result that the memory is not capable of learning. As an alternative, the memory cells are realized as EEPROM cells, thereby enabling programming, which are more complicated to fabricate, however.
One advantage of the memory cell configuration according to the invention when used as an associative memory is that the GMR elements in the memory elements can be reprogrammed as often as desired during operation. Therefore, the associative memory can learn information during operation.
In accordance with a further embodiment of the invention, a differential amplifier is provided with regard to two bit lines in each case. The inputs of the differential amplifier are in each case connected to the output of the sense amplifiers of the associated bit lines. This memory cell configuration is preferably likewise used as an associative memory, the memory elements in the two bit lines which are connected to the same word line in each case being programmed complementarily with respect to one another. During read-out, there is formed on one bit line the complementary signal of the other. The output signal is formed from these complementary signals in the differential amplifier. This differential method considerably improves the interference immunity in respect of processed fluctuations.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration and its use as a magnetic RAM and as an associative memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.